1. Field of the Invention
The present invention relates generally to memory systems, and more specifically, to memory modules and memory components, such as a memory device or a memory buffer, having built-in self test functionality.
2. Discussion of the Related Art
Integrated circuit devices such as random access memories (RAMs) usually undergo device verification testing during manufacture. Typically, such verification tests are designed to detect both static and dynamic defects in a memory array. Static defects include, for example, open circuit and short circuit defects in the integrated circuit device. Dynamic defects include defects such as weak pull-up or pull-down transistors that create timing sensitive defects.
A specialized integrated circuit device tester is normally employed to perform manufacturing verification tests. For example, such an integrated circuit device tester may be used to perform read/write verification cycle tests on the memory array. Relatively low-speed (e.g., 20 MHz), low-cost integrated circuit device testers are usually sufficient for detecting static defects in the memory array. However, extremely expensive integrated device testers are needed to detect dynamic defects in very high-speed memory arrays. Such expensive high-speed integrated circuit testers increase the overall manufacturing costs for such devices. In addition, for integrated circuit devices that include large memory arrays, the cycle time required to perform such read/write tests increases in proportion to the size of the array.
Attempts to overcome some of the difficulties associated with testing integrated circuit devices have included implementing built-in self-test (BIST) circuitry. For example, an integrated circuit cache memory array may contain circuitry to perform a standard static random access memory (SRAM) 13N March test algorithm on the memory array. A state machine is typically used to generate the 13N March test algorithm along with circuitry to sample data output and to generate a signature of the results. The signature is then compared against an expected value to determine whether defects exist in the memory array. Such BIST circuitry usually enables high-speed testing while obviating expensive high-speed testers.
Unfortunately, these BIST routines have generally only been able to apply a preprogrammed test sequence on the memory array. As the process of manufacturing such a memory array evolves, manufacturing test engineers typically develop improved strategies for detecting both static and dynamic defects in the memory array.
Moreover, such improved strategies for detecting defects can only be applied to testing that occurs while the device is placed in an expensive integrated circuit device tester. Therefore, engineers have been unable to achieve the benefits of improved test strategies without the use of an expensive tester, or without redesigning the integrated circuit device. Because of the advances in memory technology, and particularly in the area of narrow high-speed buses, which typically run at speeds of about 1.6 GHz, for use with dynamic random access memory devices (DRAMs), it is very expensive to obtain a high-speed tester capable of testing a memory module or a memory component at such high operating frequencies. Therefore, the added use of expensive high-speed hardware testers increases the time required to ascertain hardware failures, not to mention greatly increasing the overall manufacturing cost of these memory modules and memory components.